Education:

Sungkyunkwan University, Architecture Suwon, 1991

Kaiserslautern Universitaet, Architecture Kaiserslautern, 1997

Kwangwoon University, Architecture PhD, 2020

 

Work experience:

1998 ~ 1999, Wondosi Architectural Design Group, Architect

1999 ~ 2000, Yang Architectural Design Group, Architecture & Interior Design Director

2001 ~ 2011, Architectural Design Group FUV,  Architecture, Interior Design, Furniture Design CEO, Design Director

2011 ~ 2016, Qingdao Technological University, Professor, Architecture Studio

2016 ~ 2018, Braitaisi Architecture Office, CEO

2011 ~ 2016, D'nos Architecture & Design Group, Architecture & Interior Design Director

2019 ~ Present, Atelier Betas, Ceo

2020 ~ Present, KIUF, Facility of Architecture Engeneering

2021 ~ Present, Ajou University in Tashkent, Architecture Professor

 

Selected Projects:

1. Oh Seok Kyu (2015) — Qingdao Kaifeng CBD, China

2. Oh Seok Kyu (2016) — Myeongdonggwan Korean Restaurant, Qingdao, China

3. Oh Seok Kyu (2016) — Sodamwon Korean Restaurant, Qingdao, China

4. Oh Seok Kyu (2017) — House in Hamyang, Korea

5. Oh Seok Kyu (2017) — Zero Energy Apartment, Seoul, Korea

6. Oh Seok Kyu (2018) — Hanoi Town House, Vietnam

7. Oh Seok Kyu (2018) — House in Goseong, Korea

8. Oh Seok Kyu (2020) — Culture Center, Jeju, Korea

9. Oh Seok Kyu (2021) — Fergana New Town Master Plan, Uzbekistan

10. Oh Seok Kyu (2022) — House in Chengdu, China

 

Education:

Kookmin University, 2002

Saint-Petersburg State University, 2005

University of Wisconsin - Madison, 2009

University of Hohenheim (PhD), 2016

 

Work experience:

1998 ~ 2000, Military Service

2002 ~ 2003, GIST (Gwangju Institute of Science and Technology, Gwangju, Korea), Research Intern

2005 ~ 2006, KIOST (Korea Institute of Ocean Science and Technology, Seoul, Korea), Research Intern

2009 ~ 2011, SSEC (Space Science Engineering Center, Madison, Wisconsin, US), Researcher

2011 ~ 2012, SMHI (Swedish Meteorological and Hydrological Institute, Sweden), Visiting Scientist Associate

2014/7 ~ 2014/9, JPL (Jet Propulsion Laboratory - NASA), Research visiting

2016 ~ 2019, KMAWRC (Korea Meteorological Administration Weather Radar Center), Researcher

2019 ~ 2021, NIMS (National Institute of Meteorological Science, Korea), Senior Researcher

2021 ~ Present, Ajou University in Tashkent, Civil System Engineering Professor

 

 

 

 

 

 

Professional Summary:

• Ph.D. in Electrical and Computer Engineering with more than 20 years of R&D experience in the industry.

• Experience in all stages of the standard ASIC design flow, from architecture, logic, and circuit design to validation.

• Teaching assistant for two semesters (nominated for Best Teaching Assistant) and instructor for industry and local community programs for several years.

• Experience leading multifunctional design and development teams through cross-disciplinary collaboration and project execution.

• Hands-on experience in ASIC, SoC, VLSI, and embedded system design, including architecture, logic, circuit, and layout design.

• Experience in developing high-performance CPUs, MCUs, and DSP systems, with a strong background in solid-state device physics.

• Experience in designing SSD (solid-state drive) controllers, from architecture, logic, and circuit design to validation.

• Experience implementing signal processing and ECC algorithms (LDPC) for NAND flash memory adaptation.

• Research interests include smart, energy-efficient, and variation-resilient integrated systems using nanoscale technologies.
   

Education:

DSc., Tashkent, Uzbekistan, No. 007186, October 2022.

Ph.D., Purdue University, Electrical and Computer Engineering, West Lafayette, IN, USA, December 2007.
Dissertation title: Low-Power and Process-Variation-Resilient VLSI Design in Nanometer Technologies.

M.S., Korea Advanced Institute of Science and Technology (KAIST), Electrical and Electronics Engineering, Daejeon, South Korea, February 1996.
Thesis title: DCT/IDCT Processor Design.

B.S., Hanyang University, Electronics Engineering, Seoul, South Korea, February 1992.
 

Employment History:

2022 – Present
Professor, Electrical and Computer Engineering, Ajou University in Tashkent, Uzbekistan

2018 – 2021
Freelance Engineer, Multiple Locations, San Jose, USA

2016 – 2018
Fellow Engineer (Vice President), SK Hynix Memory Solutions, California, USA

2010 – 2016
Principal Engineer (SoC Director), Samsung Electronics Co., South Korea

2007 – 2010
Special Circuit Designer (Team Lead), Intel Corporation, Hillsboro, OR, USA

2004 – 2005
Intern, Qualcomm Inc., San Jose, CA, USA

1995 – 2001
Senior Engineer, LG Semiconductor (acquired by SK Hynix), Seoul, South Korea

 

Project Experience:

Ajou University in Tashkent, Uzbekistan (January 2022 – Present)

Title and Role: Professor, teaching Electrical and Computer Engineering to ECE students.

SK Hynix Memory Solutions, San Jose, CA, USA (April 2016 – May 2018)

Title and Role: Fellow (Vice President), SoC Design and Architecture.

Samsung Electronics, Seoul, South Korea (October 2010 – January 2016)

Title and Role: Principal Engineer, Engineering Director, SoC Design and Development.

Intel Corporation, Hillsboro, OR, USA (March 2008 – August 2010)

Title and Role: Special Design Engineer, Team Lead, CPU Design and Mixed-Signal Design.

Qualcomm Inc., San Diego, CA, USA (July 2004 – June 2005)

Title and Role: Intern, R&D.

LG Semiconductor (acquired by SK Hynix), Seoul, South Korea (June 1995 – July 2001)

Title and Role: Staff Design Engineer, ASIC Design.

 

Patents:

1. Myeong-Eun Hwang and Insuh Hwang, “High Bandwidth Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 19/259,522, filed July 3, 2025 (CIP).

2. Myeong-Eun Hwang and Insuh Hwang, “Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 12,356,724, granted July 8, 2025.

3. Myeong-Eun Hwang et al., KR Patent 10-2023-0151895, granted July 11, 2024.

4. Myeong-Eun Hwang, US Patent 17/962,578, October 10, 2022.

5. Myeong-Eun Hwang, KR Patent 10-2022-011518, September 13, 2022.

6. Myeong-Eun Hwang and Do Kim, US Patent 17/369030, July 7, 2021.

7. KR Patent 10-2021-0099144, July 28, 2021.

• More than 20 additional international patents.
   

Membership of Professional Bodies:

• IEEE Member
• IEEE ISCAS Reviewer
• ACM/IEEE DATE Reviewer
• IEEE TCAS, TED, JSSC Reviewer
   

Subjects Taught:

• Electromagnetic Fields
• Logic Design
• Microelectronics
• Systems and Signals
• Data Structures and Algorithms
• Advanced Semiconductor Chip Design
• Advanced Engineering Mathematics
• C Language
• Capstone I/II
• Introduction to Artificial Intelligence

  
  I am a PhD from Purdue University, IN, USA, and worked for several major semiconductor companies such as Intel (OR, USA), Qualcomm (CA, USA), Samsung Electronics (S. Korea) as a semiconductor chip design engineer and executive for 20+ years with 60+ international papers and patents.

  I am also a Doctor of Sciences honorably granted by the UZ government.

 

Publications:

1. Myeong-Eun Hwang, “Energy Efficiency and Sustainability of Adaptive Intelligent Battery Management Technologies for EVs and ESSs”, E3S Web of Conferences, Vol. 574, October 2024.

2. Myeong-Eun Hwang, “Over-Provisioning and Wear-Leveling in Battery Management Systems for Electric Vehicles”, ICEE-CCA 2023, p. 85, Tashkent, Uzbekistan, August 2024.

3. Myeong-Eun Hwang, “Hydrogen Production from Hydrides Using the Resonance Effects of Electromagnetic Waves”, ICEE-CCA 2023, p. 150, Tashkent, Uzbekistan, August 2023.

4. Myeong-Eun Hwang, “Battery Management System and Battery Cell Array”, EV Magazine, submitted for online publication in August 2023.

5. Myeong-Eun Hwang and Sungoh Kwon, “A 0.94 μW 611 kHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90 nm CMOS”, Electronics, MDPI, August 2019.

• More than 60 additional international publications.