Education

Sungkyunkwan University, Architecture Suwon, 1991

Kaiserslautern Universitaet, Architecture Kaiserslautern, 1997

Kwangwoon University, Architecture PhD, 2020

Work experience

1998 ~ 1999, Wondosi Architectural Design Group, Architect

1999 ~ 2000, Yang Architectural Design Group, Architecture & Interior Design Director

2001 ~ 2011, Architectural Design Group FUV,  Architecture, Interior Design, Furniture Design CEO, Design Director

2011 ~ 2016, Qingdao Technological University, Professor, Architecture Studio

2016 ~ 2018, Braitaisi Architecture Office, CEO

2011 ~ 2016, D'nos Architecture & Design Group, Architecture & Interior Design Director

2019 ~ Present, Atelier Betas, Ceo

2020 ~ Present, KIUF, Facility of Architecture Engeneering

2021 ~ Present, Ajou University in Tashkent, Architecture Professor

1. Oh Seok Kyu. (2015), Qingdao Kaifeng CBD in China.

2. Oh Seok Kyu. (2016), Qingdao Korean Restaurant Myeingdongkwan in China.

3. Oh Seok Kyu. (2016). Qingdao Korea Restaurant Sodamwon in China.

4. Oh Seok Kyu. (2017). House in Hamyang.

5. Oh Seok Kyu. (2017). Zero Enery Apartment in Seoul.

6. Oh Seok Kyu. (2018). Hanoi Town House in Bietnam.

7. Oh Seok Kyu. (2018). House in Goseong.

8. Oh Seok Kyu. (2020). Culture Center in Jeju.

9. Oh Seok Kyu. (2021). Fergana New Town Master plan in Uzbekistan.

10. Oh Seok Kyu. (2022). House in Chengdo.

Education

Seoul National University (Republic of Korea), 1979

Pennsylvania State University State College (USA), 1984

Doctor of Philosophy, Virginia Polytechnic Institute and State University (USA), 1988 

Work experience

1988 ~ 1992, Assistant Professor, Department of Mechanical Engineering, Naval Postgraduate School (USA).

1992 ~ 2000, Assistant Professor, Department of Civil Engineering, Ajou University (Republic of Korea).  

2000 ~ Present, Professor, Department of Civil Engineering, Ajou University (Republic of Korea).

2021 ~ Present, Dean, Department of Civil Systems Engineering, Ajou University in Tashkent.

1. Yung Seok Shin. (2002). “Optimal Design of Composite Beams Considering Elastic Buckling Constraints,” KSCE.

2. Yung Seok Shin. (2002). “Optimal Tension Forces of Multi-step Prestressed Composite Girders Using Commercial Rolled Beams,” KSCE.

3. Yung Seok Shin. (2001). “An interval method for global structural optimization,” 4th symposium on ISSMO, Dalian, China.

4. Yung Seok Shin. (2000). “Optimal Design of Plate-Girder Bridges for Korean High speed Rail,” ISSMO 8th symposium on MAO, Long Beach, CA, U.S.A.

5. Yung Seok Shin. (1993). "Optimal Design of Stiffened Laminated Plates Using a Homotopy Method," KSME Journal, Vol. 7, No. 4, pp. 399-407.

6. Yung Seok Shin. (1992). “A Homotopy Method for Optimal Design Using an Envelope Function,” The 33rd AIAA/ASME/ASCE/AHS Structures Structural Dynamics and Materials (SDM) Conference.

7. Yung Seok Shin. (1991). "Stresses in Solder Joints of Electronic Packages," Naval Postgraduate School Report NPS-ME92-001.

Self-Introduction

"I am a PhD from Purdue University, IN, USA, and worked for several major semiconductor companies such as Intel (OR, USA), Qualcomm (CA, USA), Samsung Electronics (S. Korea) as a semiconductor chip design engineer and executive for 20+ years with 60+ international papers and patents.

I am also a Doctor of Sciences honorably granted by the UZ government."

HILIGHTS of EXPERIENCE

• PhD in Electrical and Computer Engineering with more than 20 years of physical R&D experience in industry;
• Experience in all design stages of the standard ASIC flow from architecture, logic, & circuit design to validation;
• TA for two semesters (nominated for the best TA), instructor for industry/local community for several years;
• Lead multifunctional design & development teams with cross-disciplinary collaboration in project execution;
• ASIC/SoC/VLSI/Embedded system hands-on design performing architecture, logic, circuit, layout design;
• Develop world-best CPUs, MCUs, and DSP systems with strong background in solid state device physics;
• Design world-best SSD (solid-state drive) controllers from architecture, logic, circuit design to validation;
• Implement signal processing and ECC algorithms (LDPC) for adaptation of NAND flash memory; and
• Research on smart, energy-efficient, and variation resilient integrated systems in nano-scale technologies.

EDUCATION

DSc. Tashkent, Uzbekistan, No. 007186, Oct. 2022.

Ph.D. Purdue University, Electrical & Computer Engineering, West Lafayette IN, USA, Dec. 2007.
Title of thesis : Low power and process variation resilient VLSI design in nanometer technologies

M.S. Korea Advanced Institute of Science and Technology (KAIST), Electrical & Electronics Engineering,
Daejon, South Korea, Feb. 1996.
Title of thesis : DCT/IDCT processor design

B.S. Hanyang University, Electronics Engineering, Seoul, South Korea, Feb. 1992.

EMPLOYMENT HISTORY

2022 - Current
Professor, ECE, Ajou University in Tashkent, Uzbekistan

2018 – 2021
Freelancer, Multiple locations, San Jose, USA

2016 – 2018
Fellow Engineer (VP), SK Hynix Memory Solutions, CA, USA

2010 – 2016
Principal Engineer (SoC Director), Samsung Electronics Co., S. Korea

2007 – 2010
Special Circuit Designer (Team Lead), Intel Corp., Hillsboro, OR, USA

2004 – 2005
Intern, Qualcomm Inc., San Jose, CA, USA

1995 – 2001
Senior Engineer, LG Semiconductor (acquired by SK Hynix), Seoul, S. Korea

PROJECT EXPERIENCE

Ajou University in Tashkent, UZ (Jan. 2022 – Current)

Title & Role: Professor, Lecturing Electrical and Computer engineering to ECE students

SK Hynix Memory Solutions, San Jose, CA, USA (April 2016 – May 2018)

Title & Role: Fellow (Vice President), SoC design & architecture
 

Samsung Electronics, Seoul, South Korea (Oct. 2010 – Jan. 2016)

Title & Role: Principal Engineer, Engineering Director, SoC design & development

Intel Corp., Hillsboro, OR, USA (March 2008 – Aug. 2010)

Title & Role: Special Design Engineer, Team Lead, CPU design & Mixed-signal design
 

Qualcomm Inc., San Diego, CA, USA (July 2004 – June 2005)

Title & Role: Intern, R&D

LG Semiconductor (acquired by SK Hynix), Seoul, South Korea (June 1995 – July 2001)

Title & Role: Staff design engineer, ASIC design
 

PATENTS

1. Myeong-Eun Hwang and Insuh Hwang, “High Bandwidth Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 19/259,522, applied on July 3, 2025 (CIP).

2. Myeong-Eun Hwang and Insuh Hwang, “Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 12,356,724, granted July 8, 2025.

3. Myeong-Eun Hwang et al., KR Patent 10-2023-0151895, granted July 11, 2024.

4. Myeong-Eun Hwang, US Patent 17/962,578, Oct. 10, 2022.

5. Myeong-Eun Hwang, KR Patent 10-2022-011518, Sept. 13, 2022.

6. Myeong-Eun Hwang and Do Kim, US Patent 17/369030, July 7, 2021.

       7. KR Patent 10-2021-0099144, July 28, 2021.

      * Other more than 20 international patents

PUBLICATIONS

1–19. (IEEE TED, TCAS, VLSI, ISLPED, DATE, CICC, MDPI Electronics, EV Magazine и др. — весь список публикаций без сокращений)

1. Myeong-Eun Hwang, “Energy Efficiency and Sustainability of Adaptive Intelligent Battery Management Technologies for EVs and ESSs”, E3S Web Conf., Vol. 574, Oct. 2024. https://doi.org/10.1051/e3sconf/202457405008
2. Myeong-Eun Hwang, “Over-provisioning and Wear-leveling in Battery Management Systems for Electric Vehicles”, ICEE-CCA 2023, p85, Tashkent, Uzbekistan, August 2024.
3. Myeong-Eun Hwang, “Hydrogen Production from Hydrides Using the Resonance Effects of Electromagnetic Waves”, ICEE-CCA 2023, p150, Tashkent, Uzbekistan, August 2023.
4. Myeong-Eun Hwang, “Battery Management System and Battery Cell Array”, EV magazine, submitted for online publication in August 2023.
5. Myeong-Eun Hwang and Sungoh Kwon, “A 0.94W 611KHz In-Situ Logic Operation in Embedded DRAM Memory Arrays in 90nm CMOS”, Electronics, MDPI, publisher of open-access scientific journals, Aug. 2019.

* Other more than 60 international publications

MEMBERSHIP OF PROFESSIONAL BODIES

IEEE Member
IEEE ISCAS Reviewer
ACM/IEEE DATE Reviewer
IEEE TCAS, TED, JSSC Reviewer

SUBJECTS TAUGHT

Electromagnetic Fields
Logic Design
Microelectronics
Systems and Signals
Data Structure and Algorithm
Advanced Semiconductor Chip Design
Advanced Engineering Mathematics
C Language
Capstone I/II
Introduction to AI