Education

Sungkyunkwan University, Architecture Suwon, 1991

Kaiserslautern Universitaet, Architecture Kaiserslautern, 1997

Kwangwoon University, Architecture PhD, 2020

Work experience

1998 ~ 1999, Wondosi Architectural Design Group, Architect

1999 ~ 2000, Yang Architectural Design Group, Architecture & Interior Design Director

2001 ~ 2011, Architectural Design Group FUV,  Architecture, Interior Design, Furniture Design CEO, Design Director

2011 ~ 2016, Qingdao Technological University, Professor, Architecture Studio

2016 ~ 2018, Braitaisi Architecture Office, CEO

2011 ~ 2016, D'nos Architecture & Design Group, Architecture & Interior Design Director

2019 ~ Present, Atelier Betas, Ceo

2020 ~ Present, KIUF, Facility of Architecture Engeneering

2021 ~ Present, Ajou University in Tashkent, Architecture Professor

1. Oh Seok Kyu. (2015), Qingdao Kaifeng CBD in China.

2. Oh Seok Kyu. (2016), Qingdao Korean Restaurant Myeingdongkwan in China.

3. Oh Seok Kyu. (2016). Qingdao Korea Restaurant Sodamwon in China.

4. Oh Seok Kyu. (2017). House in Hamyang.

5. Oh Seok Kyu. (2017). Zero Enery Apartment in Seoul.

6. Oh Seok Kyu. (2018). Hanoi Town House in Bietnam.

7. Oh Seok Kyu. (2018). House in Goseong.

8. Oh Seok Kyu. (2020). Culture Center in Jeju.

9. Oh Seok Kyu. (2021). Fergana New Town Master plan in Uzbekistan.

10. Oh Seok Kyu. (2022). House in Chengdo.

Education

Seoul National University (Republic of Korea), 1979

Pennsylvania State University State College (USA), 1984

Doctor of Philosophy, Virginia Polytechnic Institute and State University (USA), 1988 

Work experience

1988 ~ 1992, Assistant Professor, Department of Mechanical Engineering, Naval Postgraduate School (USA).

1992 ~ 2000, Assistant Professor, Department of Civil Engineering, Ajou University (Republic of Korea).  

2000 ~ Present, Professor, Department of Civil Engineering, Ajou University (Republic of Korea).

2021 ~ Present, Dean, Department of Civil Systems Engineering, Ajou University in Tashkent.

1. Yung Seok Shin. (2002). “Optimal Design of Composite Beams Considering Elastic Buckling Constraints,” KSCE.

2. Yung Seok Shin. (2002). “Optimal Tension Forces of Multi-step Prestressed Composite Girders Using Commercial Rolled Beams,” KSCE.

3. Yung Seok Shin. (2001). “An interval method for global structural optimization,” 4th symposium on ISSMO, Dalian, China.

4. Yung Seok Shin. (2000). “Optimal Design of Plate-Girder Bridges for Korean High speed Rail,” ISSMO 8th symposium on MAO, Long Beach, CA, U.S.A.

5. Yung Seok Shin. (1993). "Optimal Design of Stiffened Laminated Plates Using a Homotopy Method," KSME Journal, Vol. 7, No. 4, pp. 399-407.

6. Yung Seok Shin. (1992). “A Homotopy Method for Optimal Design Using an Envelope Function,” The 33rd AIAA/ASME/ASCE/AHS Structures Structural Dynamics and Materials (SDM) Conference.

7. Yung Seok Shin. (1991). "Stresses in Solder Joints of Electronic Packages," Naval Postgraduate School Report NPS-ME92-001.

HILIGHTS of EXPERIENCE

• PhD in Electrical and Computer Engineering with more than 20 years of physical R&D experience in industry;
• Experience in all design stages of the standard ASIC flow from architecture, logic, & circuit design to validation;
• TA for two semesters (nominated for the best TA), instructor for industry/local community for several years;
• Lead multifunctional design & development teams with cross-disciplinary collaboration in project execution;
• ASIC/SoC/VLSI/Embedded system hands-on design performing architecture, logic, circuit, layout design;
• Develop world-best CPUs, MCUs, and DSP systems with strong background in solid state device physics;
• Design world-best SSD (solid-state drive) controllers from architecture, logic, circuit design to validation;
• Implement signal processing and ECC algorithms (LDPC) for adaptation of NAND flash memory; and
• Research on smart, energy-efficient, and variation resilient integrated systems in nano-scale technologies.

EDUCATION

DSc. Tashkent, Uzbekistan, No. 007186, Oct. 2022.

Ph.D. Purdue University, Electrical & Computer Engineering, West Lafayette IN, USA, Dec. 2007.
Title of thesis : Low power and process variation resilient VLSI design in nanometer technologies

M.S. Korea Advanced Institute of Science and Technology (KAIST), Electrical & Electronics Engineering,
Daejon, South Korea, Feb. 1996.
Title of thesis : DCT/IDCT processor design

B.S. Hanyang University, Electronics Engineering, Seoul, South Korea, Feb. 1992.

EMPLOYMENT HISTORY

2022 - Current
Professor, ECE, Ajou University in Tashkent, Uzbekistan

2018 – 2021
Freelancer, Multiple locations, San Jose, USA

2016 – 2018
Fellow Engineer (VP), SK Hynix Memory Solutions, CA, USA

2010 – 2016
Principal Engineer (SoC Director), Samsung Electronics Co., S. Korea

2007 – 2010
Special Circuit Designer (Team Lead), Intel Corp., Hillsboro, OR, USA

2004 – 2005
Intern, Qualcomm Inc., San Jose, CA, USA

1995 – 2001
Senior Engineer, LG Semiconductor (acquired by SK Hynix), Seoul, S. Korea

TEACHING EXPERIENCE

2022 - Current
Professor lecturing on Electronics and DX

2011 - 2012
Lecturer on VLSI Circuit Design, Samsung Electronics, S. Korea

Spring 2005
Teaching Assistant, Design of Analog CMOS Integrated Circuits, Purdue Univ., IN, USA

Fall 2004
Teaching Assistant (Best TA nominated), Digital Integrated Circuits, Purdue Univ., IN, USA

2003
Instructor, Science and Technology for local middle school students, Hillsboro, OR, USA

2002
Supervisor, Korean American Students Association, Math competitions for the gifted students

PROJECT EXPERIENCE

Ajou University in Tashkent, UZ (Jan. 2022 – Current)

Title & Role: Professor, Lecturing Electrical and Computer engineering to ECE students

• Green hydrogen production, Battery Management System for Electric Vehicles & Energy Storage Systems

• Zero or Negative energy harvest (long-term project)

Solo Proprietorship, multiple locations, USA (June 2018 – Dec. 2021)

Title & Role: Freelancer, Semiconductor chip design, ASIC/SoC & architecture

• KR Patent applied on hydrogen production

• KR/US Patents applied/registered on energy-efficient battery systems for EV & energy storage systems

• Hardware accelerators developed for Machine Learning at Facebook

• AR/VR systems designed in Amazon Lab

• Paper published on in-situ logic operation within embedded memories based on non-Von Neumann computer architecture for big data and deep learning applications

• Working on new and smart features for future SSD and storage systems

SK Hynix Memory Solutions, San Jose, CA, USA (April 2016 – May 2018)

Title & Role: Fellow (Vice President), SoC design & architecture

• Development of high-performance & low-power SSD (Solid State Drive) controllers at the SoC level

• PCIe (Peripheral Component Interconnect Express) Gen4 as well as Gen 1, 2, and 3 support

• Flash memory based NVMe (Non-Volatile Memory Express) 1.3 protocol support

• Low-power variation-resilient design methodology development

Samsung Electronics, Seoul, South Korea (Oct. 2010 – Jan. 2016)

Title & Role: Principal Engineer, Engineering Director, SoC design & development

• Design and development of the world's best >1M IOPS and <5W enterprise SSD controllers

• PCIe Gen3 as well as Gen 1 & 2 support

• 2D/3D NAND flash memory based NVMe 1.2b protocol support

• Low-Power PVT (Process, Voltage & Temperature) variation tolerant design methodology applied

Intel Corp., Hillsboro, OR, USA (March 2008 – Aug. 2010)

Title & Role: Special Design Engineer, Team Lead, CPU design & Mixed-signal design

A. Feb. 2009 – Aug. 2010:

• Design and development of world's best mainstream microprocessors (Nehelm, Westmere, and Haswell)

• Deliver 14 PLL-enclosed mixed-signal full-custom-design blocks as a project leader (PL)

• Design of clock trees across the entire chip as a workgroup member

B. March 2008 – Feb. 2009:

• Design of digital IP blocks in a CPU which interface with chip-outside world as a circuit engineer

• Perform all design-related works such as functionality verification, formality check, timing closure, power optimization and noise analysis

• Improvement of smart and low-power design methodologies that were adopted in product design

• Design and verification of control synthesis blocks, optimized from the viewpoint of performance, dynamic and leakage power consumption, signal and power integrity, and area overhead as well

Qualcomm Inc., San Diego, CA, USA (July 2004 – June 2005)

Title & Role: Intern, R&D

• Feasibility test and process characterization over two IBM nanometer technologies (90nm and 65nm)

• Analytical analysis and proposition of a gate-interconnect interdependent delay model applicable to sub-100nm technologies

• With test chips, demonstrated effectiveness, fidelity, & accuracy of the proposed interdependent delay model

LG Semiconductor (acquired by SK Hynix), Seoul, South Korea (June 1995 – July 2001)

Title & Role: Staff design engineer, ASIC design

• Logic design and validation of high-performance low-power DSPs in Verilog HDL

• Development of MPACT media processor

• Logic design of USB embedded & non-embedded MCUs

• Architecture & RTL design of high-performance low-power MCUs

• BUS matrix design in Central Bus Controller

PATENTS

1. Myeong-Eun Hwang and Insuh Hwang, “High Bandwidth Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 19/259,522, applied on July 3, 2025 (CIP).

2. Myeong-Eun Hwang and Insuh Hwang, “Double-Sided Integrated Circuit Die and Integrated Circuit Package Including the Same”, US Patent 12,356,724, granted July 8, 2025.

3. Myeong-Eun Hwang et al., KR Patent 10-2023-0151895, granted July 11, 2024.

4. Myeong-Eun Hwang, US Patent 17/962,578, Oct. 10, 2022.

5. Myeong-Eun Hwang, KR Patent 10-2022-011518, Sept. 13, 2022.

6. Myeong-Eun Hwang and Do Kim, US Patent 17/369030, July 7, 2021.

7. KR Patent 10-2021-0099144, July 28, 2021.
   8–26. (Battery Management System, storage, latch devices, delay estimation, multithreading, package design — полный перечень как в PDF, 26 патентов)

PUBLICATIONS

1–19. (IEEE TED, TCAS, VLSI, ISLPED, DATE, CICC, MDPI Electronics, EV Magazine и др. — весь список публикаций без сокращений)

SKILLS

Operating Systems: LINUX/UNIX, MS Windows
Programming: Verilog, Matlab, SPICE, Python, C
EDA Tools: Synopsys, Cadence, Mentor Graphics
FPGA & Emulation: Xilinx, Palladium, Veloce
Leadership, SoC/ASIC design, device physics, ML fundamentals

HONORS AND AWARDS

Intel Corp. Awards (2009–2010)
Best TA nominated (2005)
RA/TA Scholarships
Full Scholarship (Korea)
Honor Student Awards

MEMBERSHIP OF PROFESSIONAL BODIES

IEEE Member
IEEE ISCAS Reviewer
ACM/IEEE DATE Reviewer
IEEE TCAS, TED, JSSC Reviewer

SUBJECTS TAUGHT

Electromagnetic Fields
Logic Design
Microelectronics
Systems and Signals
Data Structure and Algorithm
Advanced Semiconductor Chip Design
Advanced Engineering Mathematics
C Language
Capstone I/II
Introduction to AI